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FPGA implemetation of a cache controller with configurable scratchpad space
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| Identifier | 000342586 | |||
| Title | FPGA implemetation of a cache controller with configurable scratchpad space | |||
| Alternative Title | Υλοποίηση σε FPGA ενός ελεγκτή κρυφής μνήμης με ρυθμιζόμενο χώρο SRAM | |||
| Author | Νικηφόρος, Γιώργος | |||
| Thesis advisor | Κατεβαίνης, Μανόλης | |||
| Abstract |
We designed and implemented a Cache Controller with configurable Scratchpad space for multi-core systems that serves the needs for interprocessor communication (IPC) of future CMPs. The proposed controller reconciles cacheable and scratchpad styles of communication in order to support hardware operations such as shipping blocks of data (either streaming, or messages, or cache lines) and detecting events and responding to them(either send/receive events, or cache miss), as the demands of new applications require. Specifically, an FPGA-based prototype is implemented, which constitutes a node of a multicore chip with a cache controller which manipulates scratchpad regions also. The design takes advantage of the MicroBlaze softcore that is supported in the FPGA fabric. We implement external integrated L2 Cache-Scratchpad memory equipped with way prediction techniques and DMA functionalities through a Network Interface tightly coupled to the second level of memory hierarchy. Our Design consumes one fifth of the resources in a medium-size FPGA. The design is 8% more efficient than the sum of two distinct controllers of cache and Network Interface. We evaluate the performance of the system by using both simulations and custom software benchmarks running on MicroBlaze. Our custom benchmarks simulate basic operations found commonly in programs. |
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| Language | English | |||
| Issue date | 2009-04-02 | |||
| Collection | School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses | |||
| Type of Work--Post-graduate theses | ||||
| Views | 580 | |||
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