References
- All95
-
Quantum Flow Control Alliance.
Quantum Flow Control: A Cell-Relay Protocol Supporting
an Available Bit Rate Service.
URL: http://www.qfc.org, July 1995.
Version 2.0.
- B+90
-
S. Borkar et al.
Supporting Systolic and Memory Communication in iWarp.
In Proceedings of the 17th Int. Symp. on Computer Architecture,
ACM SIGARCH, volume 18, pages 70-81, June 1990.
- CSB92
-
Anantha Chandrakasan, Samuel Sheng, and Robert Brodersen.
Low-power cmos digital design.
Journal of Solid-State Circuits, 27(4):473-484, April 1992.
- CST88
-
J. Coudreuse, W. Sincoskie, and J.S. Turner.
Guest Editorial in Broadband Packet Communications.
IEEE Journal on Selected Areas in Communications,
6(8):1452-1454, December 1988.
- D.E81
-
D.E.Knuth.
The Art of Computer Programming.
Addison-Wesley, Reading PA, 1981.
- DEI95
-
W. Denzel, A. Engbersen, and I. Iliadis.
A Flexible Shared-Buffer Switch for ATM at Gb/s Rates.
In Computer Networks & ISDN Systems, volume 27, pages
611-624. Elsevier Science B.V., 1995.
- DS87
-
W. Dally and C. Seitz.
Deadlock-Free Message Routing in Multiprocessor
Interconnection Networks.
IEEE Transactions on Computers, C-36(5):547-553, May 1987.
- Gal97
-
M. Galles.
Spider: A High-Speed Network Interconnect.
IEEE Micro, 17(1):34-39, Jan./Feb 1997.
- G.M85
-
G.Marsaglia.
A Current View of Random Number Generators.
In Computer Science and Statistics, The Interface. Elsevier
Science B.V., 1985.
- HIC95
-
IEEE Standard 1355-1995, ISO/IEC Standard 14575 DIS, Standard for
Heterogeneous InterConnect (HIC):low-cost, low-latency scalable serial
interconnect for parallel system construction, 1995.
URL: http://stdsbbs.ieee.org/groups/1355.
- JC89
-
J.P.Wade and C.G.Sodini.
A Ternary Content Addressable Search Engine.
IEEE Journal on Solid-State Circuits, 24(4):1003-1013, August
1989.
- J.M96
-
J.M.Rabaey.
Digital Integrated Circuits: A Design Perspective.
Prentice-Hall, 1996.
- KES+91
-
T. Kozaki, N. Endo, Y. Sakurai, O. Matsubara, M. Mizukami, and K. Asano.
32x32 Shared Buffer Type ATM Switch VLSI's for
B-ISDN's.
IEEE Journal on Sel. Areas in Communications, 9(8):1239-1247,
October 1991.
- Koz96
-
Christoforos E. Kozyrakis.
The Architecture, Operation and Design of the Queue
Management Block in the ATLAS I ATM Switch.
Technical Report TR-172, Institute of Computer Science - Foundation
for Research and Technology Hellas (ICS-FORTH), July 1996.
URL:
file://ftp.ics.forth.gr/tech-reports/1996/1996.TR172.QueueManagement.ps.gz.
- KSV96
-
M. Katevenis, D. Serpanos, and P. Vatsolaki.
ATLAS I: A General-Purpose, Single-Chip ATM Switch
with Credit-Based Flow Control.
In Proceedings of the Hot Interconnects IV Symposium, pages
63-73, CA, USA, August 1996. Stanford Univ.
URL:
file://ftp.ics.forth.gr/tech-reports/1996/1996.HOTI.ATLAS_I_ATMswitchChip.ps.gz.
- KVE95
-
M. Katevenis, P. Vatsolaki, and A. Efthymiou.
Pipelined Memory Shared Buffer for VLSI Switches.
In Proceedings of the ACM SIGCOMM '95 Conference, pages 39-48,
Cambridge, MA., USA, August 1995.
URL:
file://ftp.ics.forth.gr/tech-reports/1995/1995.SIGCOMM95.PipeMemoryShBuf.ps.gz.
- LeB92
-
J. LeBoudec.
The Asynchronous Transfer Mode: A Tutorial.
Computer Networks and ISDN Systems, 24(4), May 1992.
- MCLN93
-
R. Marbot, A. Cofler, J. C. Lebihan, and R. Nezamzadeh.
Integration of Multiple Bidirectional Point-to-Point
Serial Links in the Gigabits per Second Range.
In Proceedings of the Hot Interconnects I Symposium, CA, USA,
August 1993. Stanford Univ.
- MSDM94
-
M.Mascagni, S.Cuccaro, D.Pryor, and M.Robinson.
A fast, high quality, reproducible, parallel, lagged-Fibonacci
pseudorandom number generator.
Technical report, Supercomputing Research center, 17100 Science
Drive, Bowie, MD 20715, 1994.
SRC-TR-94-115.
- NC92
-
N.Troullinos and C.Stormon.
Design Issues in Static Content-Addressable Memory Cells.
Technical Report 9208, CASE Center Syracuse University, August 1992.
- PH93
-
D. Patterson and J. Hennessy.
Computer Organization: the hardware/software interface.
Morgan Kaufman Publishers, 1993.
- SIU+92
-
Katsuro Sasaki, Koichiro Ishibashi, Kiyotsugu Ueda, Kunihiro Komiyaji, et al.
A 7-ns 140mw 1-mb cmos sram with current sense amplifier.
Journal of Solid-State Circuits, 27(11):1511-1517, November
1992.
- SMS+91
-
Y. Shobatake, M. Motoyama, E. Shobakate, T. Kamitake, S. Shimizu, M. Noda, and
K. Sakaue.
A One-Chip Scalable 8 * 8 ATM Switch LSI Employing
Shared Buffer Architecture.
IEEE Journal on Sel. Areas in Communications, 9(8):1248-1254,
October 1991.
- S.S91
-
S.Sidiropoulos.
Fast packet switches for asynchronous transfer mode.
Technical Report TR-25, Institute of Computer Science - Foundation
for Research and Technology Hellas (ICS-FORTH), Heraklio,Crete,GR, August
1991.
URL: file://ftp.ics.forth.gr/tech-reports/1991/1991.TR25.Fast_packet_switches.ps.Z.
- TF88
-
Y. Tamir and G. Frazier.
High-Performance Multi-Queue Buffers for VLSI
Communication Switches.
In Proceedings of the 15th Int. Symp. on Computer Architecture,
ACM SIGARCH, volume 16, pages 343-354, May 1988.
- THY+96
-
T.Miwa, H.Yamada, Y.Hirota, T.Satoh, and H.Hara.
A 1-Mb 2-Tr/b Nonvolatile CAM Based on Flash Memory
Technologies.
IEEE Journal on Solid-State Circuits, 31(11):1601-1608,
November 1996.
- Tob90
-
F.A. Tobagi.
Fast Packet Switch Architectures for Broadband Integrated
Services Digital Networks.
In Proceedings of the IEEE, volume 78, pages 133-167, January
1990.
- TW73
-
T.G.Lewis and W.H.Payne.
Generalized Feedback Shift Register Pseudorandom Number
Algorithm.
Journal of the Association for Computing Machinery,
20(3):456-468, July 1973.
- WE93
-
N. Weste and Eshraghian.
Principles of CMOS VLSI Design - a Systems Perspective.
Addison-Wesley, 2 edition, 1993.
- W.W61
-
W.W.Peterson.
Error Correcting Codes.
MIT Press, Cambridge, Mass, 1961.
Appendix C.
Next: About this document
Up: Υλοποίηση του υποσυστήματος
Previous: Pin descriptions of full-custom
Giorgos &
Tue Jul 8 17:26:02 EET DST 1997