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Identifier

uch.csd.msc//1998glykopoulos

Title

Σχεδίαση και υλοποίηση ενός ενταμιευτή πακέτων ATM συνολικής παροχής 1.2Gbit/s που χρησιμοποιεί σύγχρονη δυναμική μνήμη

Alternative Title

Design and implementation of an 1.2Gbit/s ATM Cell Buffer using a Synchronous DRAM chip

Creator

Glykopoulos, George

Abstract

High speed networks require high throughput memories to store cells or packets. Synchronous Dynamic RAM (SDRAM) chips provide both high storage capacity and high throughput, and are thus an appropriate technology for building such cell or packet buffers. One 16Mbit SDRAM chip with a 16-bit data interface provides 40K cell storage and 1.2Gbit/s throughput when used as an ATM cell buffer. The purpose of this work is to demonstrate this capability in a working prototype, gaining familiarity with the practical details of SDRAM and SONET operation, and PCB implementation with 100MHz clocks. The prototype that was designed, manufactured and successfully tested, is an 8-layer PCB with two SONET OC-3 links (2 x 155.52Mbit/s incoming and 2 x 155.52Mbit/s outgoing throughput), interfaced to an SDRAM chip using two Altera FPGA's. The board also includes a microprocessor interface and PLL-driven clock generators/drivers.

Issue date

1998-07-01

Date available

1998-11-23

Collection

School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses

Type of Work--Post-graduate theses

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