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Identifier uch.csd.msc//2004simos
Title Σχεδίαση του Chip ενός Μεταγωγέα 32x32 Τύπου Buffered Crossbar Πακέτων Μεταβλητού Μεγέθους
Alternative Title Design of a 32x32 Variable-Packet-Size Buffered Crossbar Switch Chip
Creator Simos, Dimitris
Abstract Switches and routers are the basic building blocks of most modern interconnections and of the Internet, aiming at providing datapath connectivity, while solving output contention, the major problem of distributed multi-party communication. The latter is accomplished through buffering, access control, flow control, or datagram dropping. Modern high-end switches are called upon to provide aggregate throughputs in the terabit per-second range, which greatly challenges both their architecture and implementation technology. The aim of this work is to prove the feasibility of a novel buffered crossbar organization, operating directly on variable-size packets. Such operation, combined with distributed scheduling, removes the need for internal speedup, thus fully utilizing the incoming throughput. We proved the feasibility of this novel architecture by fully designing such a 32x32 buffered crossbar, in the form of an ASIC chip core, providing 300 Gbit/sec of aggregate bandwidth in 0.18 um technology, or higher throughput in more advanced technologies. The design was synthesized, placed, and routed, using a hierarchical ASIC flow, resulting in a 420 mm2, 6 Watt core in 0.18 um CMOS technology. In 0.13 um CMOS, area would be reduced to 200 mm2, and power consumption to 3.2 W. Power estimation showed that the majority of power is consumed in driving cross-chip wires, while memories and logic are minority consumers. Hierarchical ASIC flows are difficult to use, but became necessary due to the large size of the design. We present the detailed system design (block diagrams as well as critical circuit details), followed by a detailed description of the design flow, including its numerous intricacies and the lessons that we learnt. In particular, we describe the choice of a hierarchy that is appropriate for effective placement, routing, and timing behavior. The final placement and routing showed that the synthesis tool had underestimated the design area by 30%, due to the dominance of long (end-to-end) wires in this design.
Issue date 2004-11-01
Date available 2005-02-08
Collection   School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses
  Type of Work--Post-graduate theses
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