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Identifier

uch.csd.msc//2002kapsalis

Title

Σχεδιασμός και υλοποίηση ενός Ανα-Ροή Διαχειριστή ουρών για ένα μεταγωγέα τύπου ATM με χρήση τεχνολογίας FPGA

Alternative Title

Design and Implementation of a Per-Flow Queue Manager for an ATM Switch using FPGA technology

Creator

Kapsalis, Dimitrios S

Abstract

Advanced Switches and routers rely mostly on Dynamic RAM technology for providing large, low-cost buffer space needed due to the burstiness of Internet traffic. Quality of Service is also desirable, therefore, per flow queueing of traffic is often implemented. We designed and implemented a queue manager that supports per flow queueing of thousands of flows of ABR traffic for an ATM Switch. A large FPGA chip was used for fast development and extensive on-board testing. To avoid SRAM chip usage and lower the pin and trace count, a single SDRAM DIMM is used for storing both cells and pointers. We implemented dynamic memory allocation. Buffer preallocation and free list bypassing were used to reduce memory accesses and increase buffer bandwidth. These techniques proved essential for satisfying the switch buffer requirements. ATM Flow Control features such as EFCI and RM Relative Rate Marking has been provided for each supported flow. We used synthesizable Verilog for simulation and of the architecture instead of ALTERA AHDL, so as to achieve cross-platform compatibility. The ALTERA MaxPlus II tool has been used for synthesis and FPGA programming. We achieved a clock frequency of 35 MHz; this translates to a peak of 800 Mbps of combined incoming and outgoing throughput for the Queue Manager; the queue manager occupies 2500 FPGA Logic Elements and 2000 SRAM bits for 64K flows.

Issue date

2002-03-01

Date available

2002-04-12

Collection

School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses

Type of Work--Post-graduate theses

Views

447

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