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Identifier

000423005

Title

Quality of service framework for low power RDMA operations over cortex R5 real time microcontroller

Alternative Title

Ανάπτυξη λογισμικού βελτίωσης της ποιότητας υπηρεσιών σε μικροελεγκτή πραγματικού χρόνου για χαμηλής κατανάλωσης λειτουργίες άμεσης προσπέλασης μνήμης

Author

Τζανάκης Αρναουτάκης, Λέανδρος Μ.

Thesis advisor

Κατεβαίνης, Μανόλης
Χρυσός, Νικόλαος

Reviewer

Μπίλας, Άγγελος
Πρατικάκης, Πολύβιος

Abstract

The High Performance Computing (HPC) contributes to the progress of science and the competitiveness of global industry. Nowadays, scaling the performance of supercomputers is limited by strict power consumption constraints. Low-power servers tightly coupled with high-speed FPGA accelerators can offer a feasible solution to deal with this challenge. Along this direction, the ExaNeSt EU-funded project develops and prototypes a system composed of power-efficient ARM-based processors, tightly coupled with FPGAs. In our system, we leverage the FPGAs in order to implement a custom lowlatency interconnect that will allow computing nodes to communicate with each other as well as with fast, non-volatile, in-node storage devices. This creates the need for a sophisticated network interface to bridge the processes that run on the ARM cores with the interconnection hardware. For bulk memory-to-memory transfers, we have developed a custom low-latency multi-channel Remote Direct Memory Access (RDMA) engine, which allows processes to bypass the kernel in order to avoid the overheads of system calls and of traditional TCP/IP protocol processing. In this thesis, we have implemented in software, using a special Real Time co-processor, several stages of the RDMA protocol, including a novel transfer segmentation into blocks, per-block timeouts and retransmissions, quality-of-service (QoS), as well as end-to-end flow control and a novel protocol for fast completion notifications. The new RDMA supports per-block multipathing and selective (block-level) retransmissions, which advance InfiniBand state-of the-art RDMA. The new RDMA, including the co-processor part, which is the outcome of this thesis, and the hardware part implemented at FORTH, is now fully functional, and has been used to run real HPC applications on the ExaNeSt prototype, which consists of tens of interconnected Ultrascale+ MPSoCs. By implementing several block and transfer level functions using the co-processor, we have reduced the complexity and development time of the RDMA, without affecting its processing rate. In this thesis, we report the features that we have implemented in the co-processor, the rationale behind our design choice, and system-level performance evaluation results.

Language

English

Subject

Network interconnects

Issue date

2019-03-29

Collection

School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses

Type of Work--Post-graduate theses

Views

431

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