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Identifier 000395067
Title Accelerating stateful network packet processing using graphics hardware
Alternative Title Επιτάχυνση της επεξεργασίας πακέτων δεδομένων δικτύου με χρήση καρτών γραφικών
Author Βασιλειάδης, Γεώργιος Ιωάννη
Thesis advisor Μαρκάτος, Ευάγγελος
Reviewer Ιωαννίδης, Σωτήρης
Νικολόπουλος, Δημήτριος
Πολυχρονάκης, Μιχάλης
Μπίλας, Άγγελος
Πρατικάκης, Πολύβιος
Μαγούτης, Κωνσταντίνος
Abstract The need for differentiated services (such as firewalls, network intrusion detection/prevention systems and traffic classification applications) that lie in the core of the Internet, instead of the end points, constantly increases. These services need to perform complex packet processing operations at upper networking layers, which, unfortunately, are not supported by t raditional edge routers. To address this evolution, specialized network appliances (called "middleboxes") are deployed, which typically perform complex packet processing operations — ranging from deep packet inspection operations to packet encryption and r edundancy elimination. Packet processing implemented in software promises to enable the fast deployment of new, sophisticated processing without the need to buy and deploy expensive new equipment. In this thesis, we propose to increase the throughput of pa cket processing operations by using Graphics Processing Units (GPUs). GPUs have evolved to massively parallel computational devices, containing hundreds of processing cores that can be used for general - purpose computing beyond graphics rendering. GPUs, how ever, have a different set of constraints and properties that can prevent existing software from obtaining the improved throughput benefits GPUs can provide. This dissertation analyzes the tradeoffs of using modern graphics processors for stateful packet processing and describes the software techniques needed to improve its performance. First, we present a deep study into accelerating packet processing operations using discrete modern graphics cards. Second, we present a broa der multi - parallel stateful packet processing architecture that carefully parallelizes network traffic processing and analysis at three levels, using multi - queue network interfaces (NICs), multiple CPUs, and multiple GPUs. Last, we explore the design of a GPU - based stateful packet processing framework, identifying a modular mechanism for writing GPU - based packet processing applications, eliminating excessive data transfers as well as redundant work found in monolithic GPU - assisted applications. Our experime ntal results demonstrate that properly architecting stateful packet processing software for modern GPU architectures can improve throughput up to 5.5 times faster than on an eight - core CPU.
Language English, Greek
Subject GP GPU
Προγραμματισμός καρτών γραφικών
Issue date 2015-05-12
Collection   School/Department--School of Sciences and Engineering--Department of Computer Science--Doctoral theses
  Type of Work--Doctoral theses
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