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| Identifier |
uch.csd.msc//2005papaefstathiou |
| Title |
Σχεδίαση και Υλοποίηση Μηχανών Κατηγοριοποίησης Πακέτων Δικτύου |
| Alternative Title |
Design and Implementation of Network Packet Classification Engines |
| Creator |
Papaefstathiou, Vassilios D
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| Abstract |
Switches and routers are the most important building blocks of todays networks and the Internet. The wide spread and growth of the Internet imposes high performance and efficiency in the network infrastructures in order to support the QoS, demanded by the state-of-the-art network applications, and the ever increasing network traffic. This thesis primarily addresses the searching tasks performed by Internet routers and switches in order to forward packets and provide differentiation of services to packets belonging to particular traffic flows. Considering that these searching tasks must be performed in a per packet basis, the speed and effectiveness of the solutions to these problems determines the efficiency of the overall networks. We have proposed novel hardware based classification schemes to support QoS in multiple network layers and meet todays high speed links requirements. Initially, we propose a Hash Based Classification Engine (HBCE) to address the problem of classification in the network MAC layer (Data Link Layer). Moving to routers we developed an innovative scheme, Bitmap Oriented Strides (BOS), which faces the Longest Prefix Matching problem and supports fast lookups by efficiently managing the routing tables. Striving to enhance the granularity of service differentiation we propose a 5-dimentional packet classification scheme that leverages packet fields from higher network layers. We developed the Bloom Based Packet Classification (B2PC) scheme which is an innovative approach for decomposed packet classification that involves Bloom filter data structures. The proposed implementation of the Hash Based Classification Engine (HBCE), can support up to 64K MAC address rules at aggregate speeds of more than 50 Gbps using only 540KB of memory. Moreover, the hardware implementation of Bitmap Oriented Strides (BOS) can handle more than 90K prefixes while requires only 600KB of memory and allows routing decisions for more than 240 million packets per second. Finally, a hardware realization of the Bloom Based Packet Classification (B2PC) handles more than 4000 rules by involving 530KB of memory and can classify packets at rates greater than 8Gbps.
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| Issue date |
2005-04-01 |
| Date available |
2005-07-20 |
| Collection
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School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses
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Type of Work--Post-graduate theses
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| Views |
449 |
Σχεδίαση και Υλοποίηση Μηχανών Κατηγοριοποίησης Πακέτων Δικτύου
