Doctoral theses
Current Record: 46 of 121
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| Identifier |
000408209 |
| Title |
Java™ on Scalable Memory Architectures |
| Alternative Title |
Η Java™ σε Κλιμακώσιμες Αρχιτεκτονικές Μνημών |
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Author
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Ζακκάκ, Φοίβος Σάμι
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Thesis advisor
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Μπίλας, Άγγελος
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Reviewer
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Πρατικάκης, Πολύβιος
Κατεβαίνης, Μανόλης
Φατούρου, Παναγιώτα
Νικολόπουλος, Δημήτριος
Μαρκάτος, Ευάγγελος
Κουταβάς, Βασίλειος
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| Abstract |
The beginning of the new millennium signaled the need for new ways to keep
improving the performance of processors. The approach of increasing the frequency
as transistors got smaller and smaller is no longer viable due to the increased power-leakage and heat generation. In an effort to maintain the performance increase steady
despite the difficulties, processor manufacturers turned to multi-core computing. This
way the industry keeps taking advantage of the smaller transistors by packing more
compute elements in the same area, rather than making the circuits more complex
and increasing the frequency. However, as the number of cores increases new
challenges come up. One such challenge regards cache-coherence. Managing
hardware caches and keeping the data coherent across them is become more and
more complex and energy inefficient as the number of cores grow. To tackle this issue
hardware architects are experimenting with modular non cache coherent and partially
coherent architectures. Such architectures delegate the memory coherency to the
software.
In this thesis we study how high productivity languages can be run efficiently on such
architectures. High productivity languages, like Java, are designed to abstract away the
hardware details and allow developers to focus on the implementation of their
algorithm. Such programming languages rely on process virtual machines, like the Java
virtual machine, to provide consistent behavior across different platforms.
We focus
our work on the Java virtual machine since it is one of the most popular and widely
studied process virtual machines on top of which tens of languages are being
implemented, with the most distinguishable being Java and Scala.
Java virtual machine
implementations need to adhere to the Java language
specifications and the Java memory model. In this thesis we study the Java memory
model and present an extension of it that exposes explicit memory transfers between
caches. This extension eases the process of arguing about the adherence of a Java
virtual machine targeting a non cache coherent architecture by providing explicit rules
regarding the ordering of memory transfers in respect to other operations in an Java
execution. We prove that our extension
is complies to the original Java memory model
and allows the same optimizations.
We present a Java virtual machine design targeting non cache coherent and partially
coherent architectures. Our design aims to minimize the number of memory transfers
and messages exchanged while still adhering to the Java memory model. Our design
also takes advantage of partial coherence by sharing some structures across different
cores on the same coherence island. Based on our design we implement a Java virtual
machine and evaluate it on an emulator of a non cache coherent architecture. The
results show that our implementation scales up to 500 of cores and its scalability is
comparable to that of the state of the art Java virtual machine running on a cache-coherent architecture.
Last but not least we model our implementation in the operational semantics of a Java
core calculus that we define for this purpose. We then prove that these operational
semantics produce only well-formed executions according to the Java memory model.
Since the operational semantics model our implementation we argue that the latter
also produces only well-formed executions, thus it adheres to the Java memory model.
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| Language |
English |
| Issue date |
2017-03-17 |
| Collection
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School/Department--School of Sciences and Engineering--Department of Computer Science--Doctoral theses
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Type of Work--Doctoral theses
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| Permanent Link |
https://elocus.lib.uoc.gr//dlib/a/1/3/metadata-dlib-1491473546-137361-29328.tkl
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| Views |
603 |
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