Your browser does not support JavaScript!

Home    Collections    Type of Work    Post-graduate theses  

Post-graduate theses

Current Record: 7 of 4970

Back to Results Previous page
Next page
Add to Basket
[Add to Basket]
Identifier 000434171
Title Efficient scheduling of concurrently executed network packet processing applications using heterogeneous hardware
Alternative Title Αποδοτικός καταμερισμός πολλαπλών παράλληλα εκτελούμενων εφαρμογών επεξεργασίας πακέτων του διαδικτύου χρησιμοποιώντας ετερογενείς συσκευές”
Author Γιακουμάκης, Ιωάννης Μ.
Thesis advisor Ιωαννίδης, Σωτήρης
Reviewer Πρατικάκης, Πολύβιος
Δημητρόπουλος, Ξενοφώντας
Abstract Network packet processing is a field of research that has been well studied during the past decade, yet the implementation of efficient and top performing middleboxes is far from being considered trivial. The difficulties mainly derive from the multiple levels of heterogeneity that have to be addressed, such as the different types of underlying hardware architecture, each one with its own strengths and weaknesses, the diversity of the typical network applications and the interference that is observed when those are executed concurrently and compete for shared resources and the fluctuations in the network traffic rate and characteristics. In this work we identify the bottlenecks and causes of those inefficiencies and propose a scheduling schema that maps packet processing applications to heterogeneous processing devices and adjusts the mapping at real time based on the traffic fluctuations in order to sustain the best possible performance. Through the evaluation phase, we show that our system is able to detect changes and adapt in order to remain as efficient as possible in terms of throughput, latency or power consumption. Finally, we identify the limitations of our proposed system and we tackle some of them by upgrading the hardware setup and applying software optimizations. Also, we benchmark the new architecture and we show that it is capable of line rate packet processing with less power consumption and reduced end-to-end latency.
Language English
Subject Architecture computing
Functions GPU
Graphics processing units
High performance
Διαδίκτυο
Επεξεργασία
Επεξεργαστές
Ετερογενείς αρχιτεκτονικές πλατφόρμες
Εφαρμογές
Κάρτες γραφικών
Πακέτα
Υψηλή απόδοση
Issue date 2020-11-27
Collection   Faculty/Department--Faculty of Sciences and Engineering--Department of Computer Science--Post-graduate theses
  Type of Work--Post-graduate theses
Permanent Link https://elocus.lib.uoc.gr//dlib/6/5/b/metadata-dlib-1606208726-23014-18522.tkl Bookmark and Share
Views 2

Digital Documents
No preview available

No permission to view document.
It won't be available until: 2021-11-27