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Identifier

000452289

Title

Design and implementation of a massively multi-threaded RISC-V processor

Alternative Title

Σχεδίαση και υλοποίηση μαζικά πολυνηματικού επεξεργαστή RISC - V

Author

Ματζουράνης, Γεώργιος-Μιχαήλ Α.

Thesis advisor

Παπαευσταθίου, Βασίλης

Reviewer

Κατεβαίνης, Μανώλης
Πρατικάκης, Πολύβιος

Abstract

The computational requirements of modern applications have out-scaled the typical capabilities that central-processing units (CPU) can provide. One of the reasons is the massive amount of data that needs to be processed in contrast to the processing power available, as well as the number of tasks and different contexts that the main CPU has to manage. Another reason is the technological obstacles, such as the power consumption needed to reach ambitious computational performance levels. In order to address the later issues, the systems nowadays employ different types of specialized accelerators for various application domains, such as graphical processing units (GPUs), tensor processing units (TPUs), and reconfigurable hardware accelerators implemented in FPGAs. The accelerators are programmed, accessed, and used through different programming models and toolchains that try to maximize the utilization of the available resources. Currently some of the most popular programming models for accelerators are OpenCL and CUDA, where the main program runs on a host CPU and spawns computational kernels that are off-loaded for execution on the accelerator devices, such as GPUs. For several categories of applications, this results in substantial performance gains and energy savings, since the most important parts of the program are executed in the specialized and optimized accelerator devices. This thesis contributes with the design and implementation of a massively multi-threaded, in-order superscalar core, Matzic, that acts as an accelerator capable of supporting OpenCL-like and CUDA-like programming models. Matzic uses the open RISC-V instruction set architecture (ISA) that is becoming increasingly popular in the recent years. The core maintains contexts for up-to 256 threads, can issue up-to 4 independent instructions per thread in each cycle and contains 7 execution clusters with different types of execution units. The core can also issue up-to 512 outstanding memory operations. We implement and verify Matzic using SystemVerilog RTL and evaluate performance via RTL simulation and bare metal code that is compiled using the GNU RISC-V toolchain. Furthermore, we evaluate the resource utilization of the design on a Xilinx Kintex Ultrascale FPGA. Finally, we test and verify Matzic on an FPGA design that contains an CVA6 (Ariane) RISC-V CPU, that works as the main processor and runs the Linux operating system (OS), 2GBytes of DDR3 DRAM for main memory, our Matzic core and an additional memory delayer which is used to study various DRAM access latencies.

Language

English

Subject

Accelerators

Computer architecture

Matzic

Muda

Social network analysis

Superscalar processor

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