Post-graduate theses
Current Record: 75 of 833
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Identifier |
000443516 |
Title |
Design and implementation of cache coherence engines for RISC-V systems |
Alternative Title |
Σχεδίαση και υλοποίηση μηχανών συνοχής κρυφών μνημών για συστήματα RISC-V |
Author
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Τοτόμης Σωτήριος Χ.
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Thesis advisor
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Κατεβαίνης, Μανώλης
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Reviewer
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Φατούρου, Παναγιώτα
Παπαευσταθίου, Βασίλης
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Abstract |
Before the multi-core era, the performance of processor chips improved mostly by continuous
increase of their clock frequency. Such high frequencies ended up in enormous power
consumption figures and heat dissipation reached non-affordable levels, especially in large-scale
systems such as Data Centers. In response to these issues, and until nowadays, manufacturers
build chips which consist of multiple processing units that restore energy efficiency, silicon costs
and improve system performance through work parallelization. In conjunction, there exists a
continuously surging interest for energy-efficient RISC architectures and particularly the opensource RISC-V Instruction Set Architecture that can further reduce the cost of multi-core chips.
Although shared memory multi-core systems tackle several problems, they also introduce
several complications. Firstly, the increased communication costs between cores and memory
while fetching instructions and data, secondly the orchestration among cores in order to maintain
coherent copies of data, associated with the same address of memory, in their private L1 and/or
L2 caches. The third important concern is the performance and energy cost of cache coherence
operations to search and locate stale copies throughout the cache hierarchy, i.e. snoop
operations. Above factors can become even more critical and challenging from the performance
point-of-view as the number of cores in a system increases. This is due to the high occupancy of
the on-chip interconnection network which is responsible for transferring requests and responses
from cores to memory, and simultaneously supporting the appropriate cache coherence protocol.
This thesis contributes with the design and implementation of cache coherence engines and
interconnect infrastructure for RISC-V systems. Specifically this work makes the following
contributions: i) the design of a hardware cache coherent on-chip interconnect based on ARM’s
ACE protocol that employs snoop filtering structures, ii) the design of the hardware infrastructure
to support cache coherence on the open-source CVA6 (former Ariane) RISC-V processor core, iii)
the implementation of a multi-core system that supports the Modified-Shared-Invalid (MSI) cache
coherence protocol.
We implement and verify our cache-coherent RISC-V multi-core design in SystemVerilog and
evaluate its performance using RTL simulation. For the evaluation we run indicative hand-made
bare metal programs and selected Litmus tests to assess its correctness. As part of the
performance measurements we present latency metrics in terms of clock cycles, clock frequency
and FPGA resource utilization.
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Language |
English |
Subject |
Cache coherence interconnects |
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Cache coherence protocols |
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Caches |
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MSI |
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Memory Consistency |
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Multicore systems |
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Δίκτυα διασύνδεσης |
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Δίκτυα συνοχής κρυφών μνημών |
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Κρυφές μνήμες |
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Πολυπύρηνα συστήματα |
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Πρωτόκολλα συνοχής κρυφών μνημών |
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Συνέπεια μνήμης |
Issue date |
2021-11-26 |
Collection
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School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses
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Type of Work--Post-graduate theses
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Permanent Link |
https://elocus.lib.uoc.gr//dlib/d/8/6/metadata-dlib-1636546017-18628-22539.tkl
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Views |
544 |