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Identifier

000441654

Title

Design and implementation of a scalable IOMMU for RISC-V architectures

Alternative Title

Σχεδίαση και υλοποίηση μιας κλιμακώσιμης μονάδας διαχείρισης μνήμης εισόδου-εξόδου για αρχιτεκτονικές RISC-V

Author

Μαστοράκης, Ιάσων Γ.

Thesis advisor

Κατεβαίνης, Μανώλης

Reviewer

Παπαευσταθίου, Βασίλης
Πρατικάκης, Πολύβιος

Abstract

Virtual memory is ubiquitous in general purpose computing systems today because it has many advantages such as simplifying memory management to ease the programmers, offering memory protection and isolation that improves security, and enabling applications to use more memory than the physically available capacity. The virtual memory is managed by the Operating System (OS) and the processors include hardware Translation Lookaside Buffers (TLBs) and Memory Management Units (MMUs) to accelerate virtual-to-physical address translation for the common case. Similarly, I/O devices with Direct Memory Access (DMA) or Graphics Processing Units (GPUs) that do not execute OS code can benefit from virtual memory. For this purpose, many modern architectures offer I/O Virtualization and protection by utilizing specialized Input-Output Memory Management Units (IOMMUs). This thesis contributes with the hardware design and implementation of an IOMMU for the rising and fast growing open RISC-V architecture ecosystem. We design a scalable IOMMU architecture that supports multiple concurrent I/O devices following the RISC-V specifications for 39- and 48-bit virtual addresses (SV39 and SV48). The design consists of two main components: (a) the Address Translation Unit (ATU) and (b) the Address Translation Controller (ATC). These components are configurable in terms of features and can be combined in several different ways to create scalable and tailored systems with many devices and varying degrees of ATU and ATC sharing. To the best of our knowledge we are among the first to design and implement an IOMMU for RISC-V systems since there are no official specifications published to date (March 2021). We implement and verify the IOMMU design in SystemVerilog and evaluate its performance using RTL simulation with synthetic traffic patterns that exercise different use cases. Moreover, we evaluate the area and frequency of our IOMMU design on a Xilinx Zynq Ultrascale+ FPGA. Finally, we create an FPGA design that includes our IOMMU and a typical DMA device and we verify its correct functionality on the real system under stress patterns.

Language

English

Subject

FPGA

Hardware

Physical Address

Virtual Address

Εικονική μνήμη

Issue date

2021-07-30

Collection

School/Department--School of Sciences and Engineering--Department of Computer Science--Post-graduate theses