| Abstract |
Moore’s law states that the total number of transistors of an integrated circuit approximately
doubles every two years. Maintaining this trend, requires tools able to cope with the everincreasing
complexity of chip design. Electronic Design Automation (EDA) has so far addressed
this problem by providing automated tools and flows which enabled designers to handle chips
consisting of more than a few millions transistors.
However, the ever shrinking of the size of transistors and interconnects, now poses new obstacles
for designers and automated EDA flows. Smaller dimension devices, although providing
more speed and less area, pose new challenges. Contemporary Deep-Sub-Micron (DSM) fabrication
processes suffer from the presence of manufacturing variations, due to unpredictability in
the exact dimensions and characteristics of transistors and wires. These variations now affect
high-level characteristics of the chips such as their speed and power consumption. Technology
vendors have always provided a number of characterizations for each circuit element at
different operating scenaria (operating corners). Nowadays, more corners are needed to account
for process variations, which adds to the complexion of achieving closure for all corners
simultaneously.
One way to mitigate this phenomenon is to integrate multiple operating scenaria into a
single, unified model, which can then be incorporated into existing flows. Statistical models
offer this capability. They can encapsulate each corner into a random distribution, which can
reflect the variation of speed and power consumption characteristics of the circuit elements. In
this case, the delay and power becomes statistical rather than deterministic. Although such
statistical models exist, their use in EDA flows has not been demonstrated. An alternative approach
for combating variations is to design circuits which include clock-less or asynchronous
speed-independent designs. These, possess the property of adjusting to their operating conditions
instead of failing for fixed constraints. This approach requires further development of
asynchronous circuits, the implementation of which has not been proven viable in EDA flows.
Currently, there is significant lack of EDA tools capable of handling asynchronous circuits,
making their use impossible in industrial designs.
In this work, we have developed and evaluated placement and post-placement optimization
algorithms, which aim to tackle the problem of process variations in contemporary EDA flows.
We present a novel placement algorithm, SCPlace, which based on a statistical timing model
in its optimization engine, alleviates the need for multi-corner placement. SCPlace is the first
vi
large-scale statistical optimization tool appearing in literature targeting placement, which is the
cornerstone of physical implementation. SCPlace exploits statistical wire delay bounds, generated
by our novel statistical slack assignment algorithms, which distribute slack according to
statistical distributions. We have also developed a post-placement statistical leakage reduction
algorithm, which is able to perform in-place statistical leakage reduction without negatively
affecting statistical delay. Our third contribution is CPlace, a fully automated placer for asynchronous,
cyclic circuits. CPlace is able to meet both performance and speed independent
constraints.
Experimental results indicate that SCPlace compares favourably with state-of-the-art, industrial
and academic placers, providing routable designs which achieve superior timing yield
computed from the resulting statistical delay distributions. Our statistical leakage reduction
flow achieves 20% average leakage reduction, without affecting the statistical delay of the preplaced
circuit. Our results also show that CPlace provides routable placements for asynchronous
circuit and superior placements compared to state-of-the-art industrial and academic placers
which cannot guarantee speed independent constraints. All three of our flows have been designed
with ease of integration into contemporary EDA flows in mind, through the use of only
industry-standard formats and by collaborating with commercial EDA tools.
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