| Abstract |
Semiconductor nanostructures, such as nanowires (NWs) and nanofins, have gained significant interest as promising elemental building blocks in nanoelectronic and nanophotonic applications. Their reduced dimensionality and high aspect ratio could enhance the miniaturization of devices and lead to high device density, decreased power consumption and high operation frequency. Among them, nanostructures of gallium nitride (GaN) have attracted much attention for the exploitation of the fundamental advantages of GaN material, such as wide direct band gap, high thermal conductivity and high breakdown voltage. This work has created new knowledge for material and device processing effects on the performance of next-generation GaN-based nanoelectronic devices, with focus on field-effect transistors (FETs) based on GaN nanofins (FinFETs) and vertical nanowires (V-NW FETs).
Initially, the experimental bottom-up processes for formation of GaN-based NWs and nanofins by Plasma Assisted Molecular Beam Epitaxy (PAMBE) are briefly discussed. The spontaneous growth of GaN NWs by PAMBE resulted to large deviations in shape and size of GaN NWs, critical parameters for the assembly of V-NW FETs, where an accurate control of the position and dimensions of NWs is necessary. Therefore, selective area growth (SAG) was studied for aligning GaN NWs on different substrates without using metal catalysts, which is accomplished by epitaxial growth on a substrate coated with a nanopatterned mask. Two different substrates were used for the SAG of GaN NWs. The growth of GaN NWs on Si (111) substrates patterned with a thermally grown SiO2 mask revealed the difficulty of filling all the Si mask windows with GaN NWs, while the grown GaN NWs exhibited larger diameter than the mask window and, in some cases, inclined direction. Nanoribbons (stripes) were also patterned on the SiO2/Si substrates, resulted to nucleation and growth of multiple GaN NWs inside each nanoribbon, instead of a compact fin material. The use of SiO2/GaN/Si substrates for the SAG of GaN NWs was also investigated. In this case, the deposition of GaN material was enhanced by the reduction of window pitch, with the pitch of 250 nm exhibiting single NW formation that follows the diameter of the mask window. However, photoluminescence (PL) experiments may suggest the formation of crystal defects in these compact NWs, possibly due to coalescence of multiple narrow NWs.
The electrical transport properties of GaN NWs grown spontaneously on Si (111) and nanopatterned SiO2/Si (111) substrates were determined, in order to evaluate the unintentional doping, and understand the surface states induced band-bending and the size effects on the conductivity of bottom-up grown GaN NWs. Conventional nanofabrication techniques were used to define multiple ohmic contacts to individual GaN NWs dispersed on SiO2/Si (111) substrates, with NW diameters ranging from 30 to 140 nm and lengths ranging from 500 to 1900 nm. Current-Voltage (I-V) measurements indicated that the apparent resistivity values of GaN NWs depended on their diameter, due to carrier depletion induced by Fermi level pinning at the lateral NW surfaces. Assuming that (EC-EF)S= 0.55 eV at the GaN NW lateral surface, a critical GaN NW diameter of ~87 nm for full depletion (punch through) of the GaN NW was calculated, in
agreement with the experimental observations. The actual resistivity of the GaN NW
crystal was then calculated by subtracting the value of the critical GaN NW diameter
from the nominal one, which resulted to resistivity values in the range of 0.01 to 0.03 Ωcm.
The estimated average doping concentration was 5.2 x 1017 cm-3.
The n-type behavior of GaN NWs was exploited in the first time, to our knowledge,
fabrication of vertical p-Si/n-GaN NW heterojunction diodes. The diodes exhibited a clear
rectifying behavior, although a non-optimized fabrication process was used, which is
promising for future nanophotonic and nanoelectronic device applications (e.g.
nanowire heterojunction solar cells).
The difficulties to develop a well-controlled SAG process for GaN NWs and
nanofins, within a reasonable time frame, shifted our research interest to a top-down
process for their formation from GaN-based films, using three processing steps:
nanopatterning by electron-beam lithography (e-beam), reactive-ion etching (RIE) and
anisotropic wet-chemical etching, based on a Tetramethylammonium hydroxide (TMAH)
solution. The TMAH treatment removes the plasma damage and smoothens the lateral
surface of the RIE-formed nanostructures, resulting to very steep and uniform GaN-based
NWs and nanofins.
The research on FinFETs was focused on the exploitation of the two-dimensional
electron gas (2DEG) channel of an AlN/GaN/AlN double barrier heterostructure, which
has been proposed and analyzed previously by the lab, for planar High Electron Mobility
Transistors (HEMTs). Transistors with metal-oxide-semiconductor (MOS) tri-gate around a
fin-shaped channel (MOS-FinHEMTs) were investigated by combining device simulations
and experimental device fabrication and characterization. A top-down process was
used for the formation of AlN/GaN/AlN nanofins. Single-fin MOS-FinHEMT devices were
fabricated for the first time, with fin width (Wfin) of 200, 350, 500 and 650 nm. Multi-fin MOSFinHEMT
devices, with channel consisting of 70 fins with Wfin = 200 nm, and conventional
planar gate MOS-HEMTs, were also fabricated for comparison. The dependence of the
threshold voltage (Vth) and the maximum drain-source current (Ids,max) on the fin width
(Wfin), as well as the effects of ohmic contact resistance, gate-drain and source-gate
distance and of the Al2O3 gate dielectric thickness (tox), were determined. Fabricated
single-fin MOS-FinHEMT devices, with tox= 20 nm, exhibited a positive shift of Vth, in
comparison to a reference planar-gate device, ranging from +0.8 V for Wfin = 650 nm to
+3.4 V for Wfin = 200 nm, due to lateral depletion of the channel by the gate contacts on
the fin sidewalls. Device simulations were used to reproduce the experimental Vth values
and also to predict the Vth of devices with narrower fins, down to Wfin=10 nm. The
boundary for normally-off operation (Vth=0 V) was determined for Wfin = 17 nm that may
increase up to 31 nm, if the tensile strain of the top AlN barrier in the fin nanostructure is
elastically relaxed. A reduction of maximum drain-source current per top gate width
(Ids,max/Wg), with decreasing Wfin in the range of 200-650 nm, may result from increased
ohmic contact resistance. However, for narrower fins, Ids,max/Wg was predicted to
decrease significantly with decreasing Wfin, due to the lateral electron depletion in the
nanofins. The Ids,max/Wg will also decrease with increasing distance between the source, gate and drain contacts for any Wfin. The Vth and Ids,max/Wg values were also calculated
for Al2O3 thickness in the range of 5 to 40 nm.
Finally, GaN V-NW FETs with a Schottky barrier gate (V-NW MESFETs) were
fabricated for the first time, using a top-down process to form GaN NWs from a PAMBE
GaN epilayer on sapphire (0001) substrate. A nanofabrication process with
comprehensive design of all processing steps was developed and validated with the
demonstration of GaN V-NW MESFETs, consisting of an array of 900 (30x30) GaN NWs with
a diameter of 100 nm and all-around gate length of 250 nm. DC I-V characteristics
exhibited normally-off operation and threshold voltage of +0.4 V, due to electron
depletion region from the all-around Schottky barrier. The I-V characteristics were
dominated by the high source and drain access resistances resulting from electron
depletion due to Fermi-level pining by surface states at the lateral GaN NW sides. A
maximum drain-source current density (Jds,max) of 330 A/cm2 and maximum
transconductance (gm,max) of 285 S/cm2 were determined from I-V measurements.
Optimization of the doping profile in the GaN epilayers, surface passivation and a selfaligned
gate process technology could address the high access resistance issue.
Overall, the research carried out within this thesis, on both GaN-based FinHEMTs
and V-NW MESFETs has established critical scientific understanding and technological
know-how for achieving further progress in the future. Essential insight was gained for the
performance capabilities of these devices, as well as the influence of nanoelectronic
device design, nanofabrication processes and material parameters.
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